Undergraduate Projects Proposed

Accelerator-Centric Operating System

Porting a Novel Algorithm to an ARM Processor

Project definition:

In this project, the students will port one of the lab’s novel algorithms to an ARM processor while focusing on efficiency and performance. To do so, the students will need to check ARM’s various components, such as its SIMD engine, L1/2/3 cache latency, and multi-core synchronization. The project will give the student hands-on on C/C++ languages.

Project requirement:

Mamat/Matam + Intro to Operating Systems courses

Supervisor(s):
Hosting Lab:
NSSL
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Task Offloading via USB3.0

Motivation:

Using co-processors for offloading tasks is a leading directive in data-center giants: instead of wasting expensive Intel CPU time, use cheap co-processors (e.g., ARM, RISC-V, etc.). While the most efficient way for sending/receiving data from/to the CPU is via PCIe (512 Gb/s), there are many cheap solutions (Raspberry PI for example) that offer relatively powerful ARM cores with USB3.0 connectivity (5Gb/s). Using these might be a good trade-off for compute-intensive tasks that do not require much data transfer between the devices. The project will give the student hands-on on C/C++ languages.

Project definition:

In this project, the students will:

(1) Write a Linux module that accepts function calls from the user space and sends them efficiently to a Raspberry-PI device using a USB3.0 connection. This will require developing an API and a communication protocol between the host and the device.

(2) Benchmark the connectivity performance between the host and the R-PI device in terms of throughput and latency.

 

Background requirements:

(1) Mamat/Matam + Into to Operating Systems courses

(2) Lab on operating systems – bonus, not mandatory

(3) Accelerated systems course – bonus, not mandatory

Supervisor(s):
Hosting Lab:
NSSL
Image for Task Offloading via USB3.0

Confidential Computing

Revizor - automatic detection of new speculative execution vulnerabilities

This project focuses on the problem of automatically detecting new speculative execution vulnerabilities on modern CPUs. These vulnerabilities, such as Spectre, Meltdown and Foreshadow, undermine the security of all existing CPU architectures, but their detection is manual and thus hard.

Our tool, Revizor [https://github.com/hw-sw-contracts/revizor] [https://www.youtube.com/watch?v=qz4OK0LMVk8] takes the first steps to automatically detect such vulnerabilities. In this project you will extend this tool to new processors (ARM or GPUs) and consider adding new features to enable more efficient testing and, possibly, find new vulnerabilities.

Supervisor(s):
Hosting Lab:
NSSL
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Programmable Networks

Distributed Stateful Applications on Programmable Switches

Recent advances in networking research have paved the path for highly performant network processors. The status quo of programmability equals low performance does not hold anymore.

Programmable data-plane switches, e.g. Intel Tofino, offer the same performance as fixed-function switches while providing data-plane programmability at the same cost.

 

Many previous projects have shown the performance benefits of in-switch acceleration, such as load balancers, network monitoring, and DDoS detectors. These applications maintain persistent state. Stateful objects such as registers, counters, and meters, exposed by the P4 language, are updated purely by the data-plane and persist across multiple packets. Effectively, allowing a packet to update the state, and the next one to read it, all at line-rate speed. Two common properties to all these projects: first, they are stateful. Second, they are designed for a single switch. However, distributed state management in the data plane is a challenging problem due to the strict limitations of the hardware.

 

We have built a few replication protocols aiming to facilitate the design of distributed stateful data-plane applications while providing well-defined consistency guarantees. We encourage you to read our paper for more details.

 

The goal of the project is to showcase these protocols by implementing distributed stateful sketch-based applications entirely in the data plane.

 

In this project, you will complete the P4 tutorials to learn the basics of the P4 behavioral model (simulator). You will then implement a data-sketch, e.g. quantile sketch, UnivMon. Then, you will learn the Tofino extensions. And, finally, you will implement and evaluate a distributed design on the real hardware.

 

We are also looking for excellent UG students and graduate students for more research-oriented directions, here we will design and optimize the core of the protocols:

  • Designing data-plane recovery protocols.

  • Optimizing inter-switch communication, e.g. selective updates and header minimization.

 

We are also open to hearing your ideas too! Do you have a different project in mind? Great! Reach out and we will discuss the details.

 

Expected duration: 1-2 semesters depending on the track.

Mandatory prerequisites:

  • C/C++ programming skills

  • A basic course in networking

Supervisor(s):
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